ELECTRICAL AND COMPUTER ENGINEERING

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	Issue Date	Title	Author(s)
1561	1992	Subband current in resonant tunneling diode	Sheng, H. ; Sinkkonen, J.
1562	19-Jul-2019	Sub-Picosecond Carrier Dynamics Induced by Efficient Charge Transfer in MoTe2/WTe2 van der Waals Heterostructures	Kyusup Lee ; Jie Li; Liang Cheng; Junyong Wang ; Dushyant Kumar ; Qisheng Wang ; Mengji Chen; Yang Wu ; Goki Eda ; Elbert E. M. Chia; Haixin Chang; Hyunsoo Yang
1563	26-Nov-2020	Sub-nW Microcontroller with Dual-Mode Logic and Self-startup for Battery-Indifferent Sensor Nodes	LIN LONGYANG ; SAURABH JAIN ; ALIOTO,MASSIMO BRUNO
1564	Mar-2006	Sub-nanosecond pulse-forming network on SiGe BiCMOS for UWB communications	Tan, A.E.-C.; Chia, M.Y.-W. ; Leong, S.-W.
1565	1-Oct-2007	Sub-micron surface patterning by laser irradiation through microlens arrays	Lim, C.S. ; Hong, M.H. ; Lin, Y. ; Chen, G.X. ; Senthil Kumar, A. ; Rahman, M. ; Tan, L.S. ; Fuh, J.Y.H. ; Lim, G.C.
1566	Aug-2006	Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure	Rana, R.S.; Liang, Z.; Garg, H.K.
1567	2012	Sub-Gaussian model based LDPC decoder for SαS noise channels	Topor, I. ; Chitre, M. ; Motani, M.
1568	2008	Sub-femto-farad capacitance-voltage characteristics of single channel gate-all-around nano wire transistors for electrical characterization of carrier transport	Zhao, H.; Rustagi, S.C.; Singh, N.; Ma, F.-J. ; Samudra, G.S. ; Budhaaraju, K.D.; Manhas, S.K.; Tung, C.H.; Lo, G.Q.; Baccarani, G.; Kwong, D.L.
9	May-2002	Sub-50 nm nanopatterning of metallic layers by green pulsed laser combined with atomic force microscopy	Huang, S.M.; Hong, M.H. ; Luk'yanchuk, B.S.; Lu, Y.F. ; Song, W.D. ; Chong, T.C.
10	2013	Sub-400 °C Si2H6 passivation, HfO2 gate dielectric, and single TaN metal gate: A common gate stack technology for In0.7Ga0.3As and Ge1-xSnx CMOS	Gong, X.; Han, G. ; Liu, B.; Wang, L.; Wang, W.; Yang, Y.; Kong, E.Y.-J.; Su, S.; Xue, C.; Cheng, B.; Yeo, Y.-C.
11	24-Apr-2007	Sub-30nm strained p-channel fin-type field-effect transistors with condensed SiGe source/drain stressors	Tan, K.-M.; Liow, T.-Y.; Lee, R.T.P. ; Chui, K.-J.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yoo, W.-J. ; Yeo, Y.-C.
12	Feb-2005	Sub-30 nm lithography with near-field scanning optical microscope combined with femtosecond laser	Lin, Y. ; Hong, M.H. ; Wang, W.J.; Law, Y.Z.; Chong, T.C.
13	2007	Sub-30 nm FinFETs with schottky-barrier source/drain featuring complementary metal silicides and fully-silicided gate for P-FinFETs	Lee, R.T.P. ; Tan, K.-M.; Liow, T.-Y.; Lim, A.E.-J.; Lo, G.-Q.; Samudra', G.S. ; Chi, D.-Z.; Yeo, Y.-C.
14	12-Jun-2022	Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing	Umesh Chand ; Mohamed M Sabry Aly; Manohar Lal ; Chen Chun-Kuei; Sonu Hooda; Shih-Hao Tsai; Zihang Fang; Hasita Veluri; Aaron Voon-Yew Thean
15	Jul-2004	Sub-100-nm current-perpendicular-to-plane sensor fabrication	Zheng, Y.K.; Li, K.B.; Qiu, J.J.; Han, G.C.; Guo, Z.B.; Zong, B.Y.; An, L.H.; Luo, P.; Liu, Z.Y.; Wu, Y.H.
16	Mar-2008	Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed	Hu, Y.; Xiang, J.; Liang, G. ; Yan, H.; Lieber, C.M.
17	2020	Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study	Jain, A.K. ; Kumar, M.J.
18	Aug-2007	Sub-0.1-eV effective Schottky-barrier height for NiSi on n-type Si (100) using antimony segregation	Wong, H.-S.; Chan, L.; Samudra, G. ; Yeo, Y.-C.
19	2007	Sub 50nm strained n-FETs formed on silicon-germanium-on-insulator substrates and the integration of silicon source/drain stressors	Wang, G.H.; Toh, E.-H.; Hoe, K.-M.; Tripathy, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C.
20	2017	Study on trapping effects in AlGaN/GaN-on-Si devices with vertical interconnect structures	Chang, T.-F; Chang, C.-Y; Huang, C.-F; Liang, Y.C ; Samudra, G.S ; Lin, R.-M