1. ScholarBank@NUS

YEO YEE CHIA

rp09882

Collaboration Map View Statistics Email Alert RSS Feed

Profile

Full Name
YEO YEE CHIA
Variants
Yeo, Y.
Yeo Y.-C.
Yeo, Y.C.
Yeo, Y.-C.
Yeo., Y.-C.
 
Main Affiliation
 
Faculty
 
Email
eleyeoyc@nus.edu.sg
 

Publications

Results 1-20 of 422 (Search time: 0.005 seconds).

Issue DateTitleAuthor(s)
12013(110)-oriented germanium-tin (Ge0.97Sn0.03) P-channel MOSFETsZhan, C.; Wang, W.; Gong, X.; Guo, P.; Liu, B.; Yang, Y.; Han, G. ; Yeo, Y.-C. 
220085 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation techniqueLiow, T.-Y.; Tan, K.-M.; Lee, R.T.P. ; Zhu, M. ; Tan, B.L.-H.; Samudra, G.S. ; Balasubramanian, N.; Yeo, Y.-C. 
3200650 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride linerAng, K.-W.; Chui, K.-J.; Chin, H.-C.; Foo, Y.-L.; Du, A.; Deng, W.; Li, M.-F. ; Samudra, G. ; Balasubramanian, N.; Yeo, Y.-C. 
42008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
52010A computational study on the device performance of graphene nanoribbon heterojunction tunneling FETs based on bandgap engineeringLam, K.-T.; Da, H. ; Chin, S.-K.; Samudra, G. ; Yeo, Y.-C. ; Liang, G. 
6Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
7Aug-2004A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gateRen, C.; Yu, H.Y. ; Kang, J.F.; Wang, X.P.; Ma, H.H.H. ; Yeo, Y.-C. ; Chan, D.S.H. ; Li, M.-F. ; Kwong, D.-L.
8Jan-2006A fast measurement technique of MOSFET Id-Vg characteristicsShen, C.; Li, M.-F. ; Wang, X.P.; Yeo, Y.-C. ; Kwong, D.-L.
92012A gate-last In0.53Ga0.47As channel FinFET with Molybdenum source/drain contactsZhang, X.; Guo, H.X.; Gong, X.; Yeo, Y.-C. 
10Feb-2008A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFETTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
11Mar-2011A high-yield HfOx-based unipolar resistive ram employing Ni electrode compatible with Si-diode selector for crossbar integrationTran, X.A.; Yu, H.Y.; Yeo, Y.C. ; Wu, L.; Liu, W.J.; Wang, Z.R.; Fang, Z.; Pey, K.L.; Sun, X.W.; Du, A.Y.; Nguyen, B.Y.; Li, M.F.
122013A new expandible ZnS-SiO2 liner stressor for n-channel FinFETsDing, Y.; Tong, X.; Zhou, Q. ; Liu, B.; Gyanathan, A.; Tong, Y.; Yeo, Y.-C. 
132011A new Ge 2Sb 2Te 5 (GST) liner stressor featuring stress enhancement due to amorphous-crystalline phase change for sub-20 nm p-channel FinFETsDing, Y.; Cheng, R. ; Koh, S.-M.; Liu, B.; Gyanathan, A.; Zhou, Q. ; Tong, Y.; Lim, P.S.-Y.; Han, G. ; Yeo, Y.-C. 
142012A new liner stressor (GeTe) featuring stress enhancement due to very large phase-change induced volume contraction for p-channel FinFETsCheng, R. ; Ding, Y.; Koh, S.-M.; Gyanathan, A.; Bai, F.; Liu, B.; Yeo, Y.-C. 
152007A new liner stressor with very high intrinsic stress (> 6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained p-channel transistorsTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
162009A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.T.; Toh, E.-H.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
17Mar-2011A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.-T.; Samudra, G. ; Yeo, Y.-C. 
182008A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistorsWong, H.-S.; Koh, A.T.-Y.; Chin, H.-C.; Lee, R.T.-P. ; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
192010A new self-aligned contact technology for III-V MOSFETsGuo, H.; Zhang, X.; Chin, H.-C.; Gong, X.; Koh, S.-M.; Zhan, C.; Luo, G.-L.; Chang, C.-Y.; Lin, H.-Y.; Chien, C.-H.; Han, Z.-Y.; Huang, S.-C.; Cheng, C.-C.; Ko, C.-H.; Wann, C.H.; Yeo, Y.-C. 
202008A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel aAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stackChin, H.-C.; Zhu, M. ; Lee, Z.-C.; Liu, X.; Tan, K.-M.; Lee, H.K.; Shi, L. ; Tang, L.-J.; Tung, C.-H. ; Lo, G.-Q.; Tan, L.-S. ; Yeo, Y.-C.