Full Name
Ha Yajun
(not current staff)
Yajun, H.A.
Yajun, H.
Ha, Y.
Jun, H.Y.


Results 1-20 of 59 (Search time: 0.005 seconds).

Issue DateTitleAuthor(s)
12015A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensorZhao W ; Pan R; Ha Yajun ; Yang Z 
22007A branch target instruction prefetchnig technique for improved performanceGade, P.R.; Paily, R.; Ha, Y. 
32013A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithmHoo, C.H.; Ha, Y. ; Kumar, A. 
42007A fast reconfigurable and area efficient encryption engine using partial reconfigurationYe, Z.; Fernando, S.D. ; Ha, Y. ; Chen, N. 
52011A hilbert curve-based delay fault characterization method for FPGAsZhang, W.; Ha, Y. 
62008A low overhead fault tolerant FPGA with new connection boxWong, F.; Ha, Y. 
7Apr-2001A new CMOS buffer amplifier design used in low voltage MEMS interface circuitsHa, Y. ; Li, M.F. ; Liu, A.Q.
82012A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAsLoke, W.T.; Ha, Y. ; Zhao, W.
92007A probabilistic approach to model resource contention for performance estimation of multi-featured media devicesKumar, A. ; Mesman, B.; Corporaal, H.; Theelen, B.; Ha, Y. 
102008An architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnectsLiu, H.; Chen, X.; Ha, Y. 
112010An area-efficient dynamically reconfigurable spatial division multiplexing Network-on-Chip with static throughput guaranteeYang, Z.J.; Kumar, A. ; Ha, Y. 
122013An area-efficient shuffling scheme for AES implementation on FPGAWang, Y.; Ha, Y. 
132008An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnectsLiu, H.; Chen, X.; Ha, Y. 
142006An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic modelPu, Y.; Ha, Y. 
15Apr-2005An embedded system to support tele-medical activityHui, N.J.; Lih, T.C.; Jun, H.Y. 
162009An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomialsMeher, P.K.; Ha, Y. ; Lee, C.-Y.
17Mar-2010An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltagePu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y. 
182009An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supplyPu, Y.; De Gyvez, J.P.; Corporaal, H.; Ha, Y. 
19Mar-2008Analyzing composability of applications on MPSoC platformsKumar, A. ; Mesman, B.; Theelen, B.; Corporaal, H.; Ha, Y. 
202010B*-tree based variability-aware floorplanningZhang, W.; Srivastava, S.; Ha, Y.