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Title: An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltage
Authors: Pu, Y.
De Gyvez, J.P.
Corporaal, H.
Ha, Y. 
Keywords: JPEG
Parallel architecture
Ultra low energy
Issue Date: Mar-2010
Citation: Pu, Y., De Gyvez, J.P., Corporaal, H., Ha, Y. (2010-03). An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltage. IEEE Journal of Solid-State Circuits 45 (3) : 668-680. ScholarBank@NUS Repository.
Abstract: We present a design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic applications. Our approach employs i) architecture-level parallelism to compensate throughput degradation, ii) a configurable VT balancer to mitigate the VT mismatch of nMOS and pMOS transistors operating in sub/near threshold, and iii) a fingered-structured parallel transistor that exploits VT mismatch to improve current drivability. Additionally, we describe the selection procedure of the standard cells and how they were modified for higher reliability in the subthreshold regime. All these concepts are demonstrated using SubJPEG, a 1.4×1.42 65 nm CMOS standard- VT multi-standard JPEG co-processor. Measurement results of the discrete cosine transform (DCT) and quantization processing engines, operating in the subthreshold regime, show an energy dissipation of only 0.75 pJ per cycle with a supply voltage of 0.4 V at 2.5 MHz. This leads to 8.3× energy reduction when compared to using a 1.2 V nominal supply. In the near-threshold regime the energy dissipation is 1.0 pJ per cycle with a 0.45 V supply voltage at 4.5 MHz. The system throughput can meet 15 fps 640×480 pixel VGA standard. Our methodology is largely applicable to designing other sound/graphic and streaming processors. © 2006 IEEE.
Source Title: IEEE Journal of Solid-State Circuits
ISSN: 00189200
DOI: 10.1109/JSSC.2009.2039684
Appears in Collections:Staff Publications

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