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|Title:||An architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnects||Authors:||Liu, H.
|Issue Date:||2008||Citation:||Liu, H.,Chen, X.,Ha, Y. (2008). An architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnects. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL : 615-618. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2008.4630022||Abstract:||Current FPGA interconnect networks occupy the major area in FPGAs. The scalability problem has become a bottleneck towards the next-generation FPGA of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. However, the architecture and its design flow have not been studied before. In this paper, we describe a novel time-multiplexed FPGA interconnect architecture and the corresponding global routing algorithm, TMRouter. Based on PathFinder, TMRouter routes the circuit with time-sharing the wire segments. Experiments show that, for 16 large MCNC benchmark circuits, the minimum channel widths and critical path delays achieved by the TMRouter are 48.70% and 11.90% in average less than those of the VPR router, respectively. © 2008 IEEE.||Source Title:||Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL||URI:||http://scholarbank.nus.edu.sg/handle/10635/69282||ISBN:||9781424419616||DOI:||10.1109/FPL.2008.4630022|
|Appears in Collections:||Staff Publications|
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