Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPL.2008.4630022
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dc.titleAn architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnects
dc.contributor.authorLiu, H.
dc.contributor.authorChen, X.
dc.contributor.authorHa, Y.
dc.date.accessioned2014-06-19T02:58:53Z
dc.date.available2014-06-19T02:58:53Z
dc.date.issued2008
dc.identifier.citationLiu, H.,Chen, X.,Ha, Y. (2008). An architecture and timing-driven routing algorithm for area-efficient fPGAs with time-multiplexed interconnects. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL : 615-618. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/FPL.2008.4630022" target="_blank">https://doi.org/10.1109/FPL.2008.4630022</a>
dc.identifier.isbn9781424419616
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69282
dc.description.abstractCurrent FPGA interconnect networks occupy the major area in FPGAs. The scalability problem has become a bottleneck towards the next-generation FPGA of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. However, the architecture and its design flow have not been studied before. In this paper, we describe a novel time-multiplexed FPGA interconnect architecture and the corresponding global routing algorithm, TMRouter. Based on PathFinder, TMRouter routes the circuit with time-sharing the wire segments. Experiments show that, for 16 large MCNC benchmark circuits, the minimum channel widths and critical path delays achieved by the TMRouter are 48.70% and 11.90% in average less than those of the VPR router, respectively. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/FPL.2008.4630022
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/FPL.2008.4630022
dc.description.sourcetitleProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
dc.description.page615-618
dc.identifier.isiutNOT_IN_WOS
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