A fast reconfigurable and area efficient encryption engine using partial reconfiguration

Abstract

Partial reconfiguration (PR) allows FPGA designers to make more efficient use of available board space. At the same time, it allows adaptive hardware algorithm to be implemented since runtime reconfiguration is now possible. One of the features of partially reconfigured FPGAs is that the size of the bitstream is proportional to the size of the reconfigured resources. Therefore reconfiguration time is shorter if partial bitstream is used. Despite the obvious benefits of PR, there is poor support for PR at the design tools and documentation levels. A recent development in the PR software tools is the introduction of the Early-Access (EA) PR design tools. However, the EA PR software tools are still in the development stage. Applications most suited for PR include reconfigurable communications and cryptographic systems. In this paper, we describe a partially reconfigurable encryption engine using the EA PR design flow. Experimental results show that when using PR over full reconfiguration, this application reduces its configuration time overhead by 300% and achieves area savings of 7%, which is limited only by the smallest partially reconfigurable module (PRM) being implemented.