Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/68796
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dc.titleA fast reconfigurable and area efficient encryption engine using partial reconfiguration
dc.contributor.authorYe, Z.
dc.contributor.authorFernando, S.D.
dc.contributor.authorHa, Y.
dc.contributor.authorChen, N.
dc.date.accessioned2014-06-19T02:53:20Z
dc.date.available2014-06-19T02:53:20Z
dc.date.issued2007
dc.identifier.citationYe, Z.,Fernando, S.D.,Ha, Y.,Chen, N. (2007). A fast reconfigurable and area efficient encryption engine using partial reconfiguration. Fourth International Conference on Information Technology and Applications, ICITA 2007 : 611-615. ScholarBank@NUS Repository.
dc.identifier.isbn0980326702
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68796
dc.description.abstractPartial reconfiguration (PR) allows FPGA designers to make more efficient use of available board space. At the same time, it allows adaptive hardware algorithm to be implemented since runtime reconfiguration is now possible. One of the features of partially reconfigured FPGAs is that the size of the bitstream is proportional to the size of the reconfigured resources. Therefore reconfiguration time is shorter if partial bitstream is used. Despite the obvious benefits of PR, there is poor support for PR at the design tools and documentation levels. A recent development in the PR software tools is the introduction of the Early-Access (EA) PR design tools. However, the EA PR software tools are still in the development stage. Applications most suited for PR include reconfigurable communications and cryptographic systems. In this paper, we describe a partially reconfigurable encryption engine using the EA PR design flow. Experimental results show that when using PR over full reconfiguration, this application reduces its configuration time overhead by 300% and achieves area savings of 7%, which is limited only by the smallest partially reconfigurable module (PRM) being implemented.
dc.sourceScopus
dc.subjectCryptographic systems
dc.subjectPartial reconfiguration
dc.subjectReconfigurable computing
dc.subjectRuntime reconfiguration
dc.typeConference Paper
dc.contributor.departmentBIOENGINEERING
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleFourth International Conference on Information Technology and Applications, ICITA 2007
dc.description.page611-615
dc.identifier.isiutNOT_IN_WOS
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