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|Title:||An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnects||Authors:||Liu, H.
|Issue Date:||2008||Citation:||Liu, H., Chen, X., Ha, Y. (2008). An area-efficient timing-driven routing algorithm for scalable FPGAs with time-multiplexed interconnects. Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08 : 275-276. ScholarBank@NUS Repository. https://doi.org/10.1109/FCCM.2008.28||Abstract:||Current FPGA interconnect networks do not scale well, and use the major part of FPGA area. This has become a bottleneck towards the next-generation FPGAs of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. But to the best of authors' knowledge, no realization of such an architecture and its design flow has been reported before. In this paper, we develop a novel time-multiplexed FPGA interconnect architecture and its global routing algorithm TMRouter. TMRouter is based on the negotiated congestiondelay algorithm. It analyzes whether congestion can be solved by time-sharing a wire segment for several nets in a congested channel. Experiments show that, for 16 MCNC benchmark circuits, their minimum channel widths and critical path delays achieved by the TMRouter are 37.50% - 57.89% and 11.90% in average less than those of the VPR router, respectively. © 2008 IEEE.||Source Title:||Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08||URI:||http://scholarbank.nus.edu.sg/handle/10635/69286||ISBN:||9780769533070||DOI:||10.1109/FCCM.2008.28|
|Appears in Collections:||Staff Publications|
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