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|Title:||An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model||Authors:||Pu, Y.
|Issue Date:||2006||Citation:||Pu, Y.,Ha, Y. (2006). An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2006 : 886-891. ScholarBank@NUS Repository.||Abstract:||Ideally, bit-width analysis methods should be able to find the most appropriate bit-widths to achieve the optimum bit-width-to-error tradeoff for variables and constants in high level DSP algorithms when they are implemented into hardware. The tradeoff enables the fixed-point hardware implementation to be area efficient but still within the allowed error tolerance. Unfortunately, almost all the existing static bit-width analysis methods are Interval Arithmetic (IA) based that may overestimate bit-widths and enable fairly pessimistic bit-width-to-error tradeoff. We have developed an automated and efficient bit-width optimization methodology that is Affine Arithmetic (AA) based. Experiments have proven that, compared to the previous static analysis methods, our methodology not only dramatically reduces the fractional bit-width by more than 35% but also slightly reduces the integer bit-width. In addition, our probabilistic error analysis method further enlarges the bit-width-to-error tradeoff. © 2006 IEEE.||Source Title:||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC||URI:||http://scholarbank.nus.edu.sg/handle/10635/69293||ISBN:||0780394518|
|Appears in Collections:||Staff Publications|
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