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Samudra,Ganesh S

rp00141

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Full Name
Samudra,Ganesh S
Variants
Samudra, G.G.
SAMUDRA, GANESH SHANKAR
Samudra', G.S.
Samudra, Ganesh S.
Samudra, Ganesh Shankar
Shankar Samudra, Ganesh
Samudra, G.S.
Samudra, Ganesh
Samudra, G.
 
Main Affiliation
 
Faculty
 
Email
eleshanr@nus.edu.sg
 

Publications

Refined By:
Date Issued:  [2000 TO 2009]
Author:  Samudra, G.

Results 1-20 of 200 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)
1Oct-2000120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limitXu, S.; Gan, K.P.; Samudra, G.S. ; Liang, Y.C.; Sin, J.K.O.
220085 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation techniqueLiow, T.-Y.; Tan, K.-M.; Lee, R.T.P. ; Zhu, M. ; Tan, B.L.-H.; Samudra, G.S. ; Balasubramanian, N.; Yeo, Y.-C. 
3200650 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride linerAng, K.-W.; Chui, K.-J.; Chin, H.-C.; Foo, Y.-L.; Du, A.; Deng, W.; Li, M.-F. ; Samudra, G. ; Balasubramanian, N.; Yeo, Y.-C. 
42006A CMOS compatible smart power synchronous rectifierLim, C.Y.; Liang, Y.C. ; Samudra, G.S. ; Balasubramanian, N.
52008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
6Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
7May-2003A dual BARC method for lithography and etch for Dual damascene with low KMukherjee-Roy, M.; Bliznetsov, V.; Samudra, G. 
8Sep-2004A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performanceJagar, S.; Singh, N.; Mehta, S.S.; Agrawal, N.; Samudra, G. ; Balasubramanian, N.
9Feb-2008A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFETTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
10Oct-2003A new approach for eliminating unwanted patterns in attenuated phase shift masksMukherjee-Roy, M.; Singh, N.; Mehta, S.S.; Samudra, G.S. 
112007A new liner stressor with very high intrinsic stress (> 6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained p-channel transistorsTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
122009A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.T.; Toh, E.-H.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
132008A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistorsWong, H.-S.; Koh, A.T.-Y.; Chin, H.-C.; Lee, R.T.-P. ; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
142008A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancementLiu, F.; Wong, H.-S.; Ang, K.-W.; Zhu, M. ; Wang, X.; Lai, D.M.-Y.; Lim, P.-C.; Tan, B.L.H.; Tripathy, S.; Oh, S.-A.; Samudra, G.S. ; Balasubramanian, N.; Yeo, Y.-C. 
152004A new surface rounding technique for deep submicron CMOS transistorTat, C.Y.; Goh, W.L.; Shenp, A.D.; Meng, T.K.; Samudra, G.S. ; Hung, C.L.
162005A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistorToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Balasubramanian, N.; Tung, C.-H.; Benistant, F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
1711-Jun-2008A pseudopotential method for investigating the surface roughness effect in ultrathin body transistorsZhu, Z.-G.; Liang, G. ; Li, M.-F. ; Samudra, G. 
18Oct-2002A simple technology for superjunction device fabrication: Polyflanked VDMOSFETGan, K.P.; Yang, X.; Liang, Y.C. ; Samudra, G.S. ; Yong, L.
192007A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancementToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Choy, S.-F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
202008A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistorsShen, C.; Ong, S.-L.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C.