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|Title:||A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistors||Authors:||Wong, H.-S.
|Issue Date:||2008||Citation:||Wong, H.-S., Koh, A.T.-Y., Chin, H.-C., Lee, R.T.-P., Chan, L., Samudra, G., Yeo, Y.-C. (2008). A new salicidation process with solid Antimony (Sb) segregation (SSbS) for achieving sub-0.1 eV effective schottky barrier height and parasitic series resistance reduction in N-channel transistors. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 36-37. ScholarBank@NUS Repository. https://doi.org/10.1109/VTSA.2008.4530787||Abstract:||We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the Ni Si/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage. © 2008 IEEE.||Source Title:||International Symposium on VLSI Technology, Systems, and Applications, Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/68928||ISBN:||9781424416158||DOI:||10.1109/VTSA.2008.4530787|
|Appears in Collections:||Staff Publications|
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