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|Title:||50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride liner||Authors:||Ang, K.-W.
|Issue Date:||2006||Citation:||Ang, K.-W.,Chui, K.-J.,Chin, H.-C.,Foo, Y.-L.,Du, A.,Deng, W.,Li, M.-F.,Samudra, G.,Balasubramanian, N.,Yeo, Y.-C. (2006). 50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride liner. Digest of Technical Papers - Symposium on VLSI Technology : 66-67. ScholarBank@NUS Repository.||Abstract:||A novel n-channel strained SOI transistor featuring siliconcarbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest IDsat observed for strained n-MOSFETs with the  channel direction. A study of the carrier transport characteristics indicate reduced channel backscattering and enhanced carrier injection velocity due to the strain effects. © 2006 IEEE.||Source Title:||Digest of Technical Papers - Symposium on VLSI Technology||URI:||http://scholarbank.nus.edu.sg/handle/10635/83301||ISBN:||1424400058||ISSN:||07431562|
|Appears in Collections:||Staff Publications|
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