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|Title:||Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode||Authors:||Zhu, S.
|Issue Date:||Oct-2004||Citation:||Zhu, S., Yu, H.Y., Chen, J.D., Whang, S.J., Chen, J.H., Shen, C., Zhu, C., Lee, S.J., Li, M.F., Chan, D.S.H., Yoo, W.J., Du, A., Tung, C.H., Singh, J., Chin, A., Kwong, D.L. (2004-10). Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode. Solid-State Electronics 48 (10-11 SPEC. ISS.) : 1987-1992. ScholarBank@NUS Repository. https://doi.org/10.1016/j.sse.2004.05.045||Abstract:||Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an Ion/Ioff ∼ 10 7-108 and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have ∼3 orders of magnitude larger I off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the Ion/Ioff ∼ 105 at low drain voltage. It can be attributed to the relatively higher barrier height (Φn) of DySi2-x/n-Si than that of PtSi/p-Si (Φp) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. © 2004 Published by Elsevier Ltd.||Source Title:||Solid-State Electronics||URI:||http://scholarbank.nus.edu.sg/handle/10635/83906||ISSN:||00381101||DOI:||10.1016/j.sse.2004.05.045|
|Appears in Collections:||Staff Publications|
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