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Samudra,Ganesh S

rp00141

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Full Name
Samudra,Ganesh S
Variants
Samudra, G.G.
SAMUDRA, GANESH SHANKAR
Samudra', G.S.
Samudra, Ganesh S.
Samudra, Ganesh Shankar
Shankar Samudra, Ganesh
Samudra, G.S.
Samudra, Ganesh
Samudra, G.
 
Main Affiliation
 
Faculty
 
Email
eleshanr@nus.edu.sg
 

Publications

Refined By:
Date Issued:  [2000 TO 2009]
Date Issued:  2008
Author:  Toh, E.-H.

Results 1-14 of 14 (Search time: 0.006 seconds).

Issue DateTitleAuthor(s)
12008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
2Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
3Jul-2008Cointegration of in situ doped silicon-carbon source and silicon-carbon I-region in P-channel silicon nanowire impact-ionization transistorToh, E.-H.; Wang, G.H.; Chan, L.; Weeks, D.; Bauer, M.; Spear, J.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
425-Apr-2008Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancementWang, G.H.; Toh, E.-H.; Tung, C.-H.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
525-Apr-2008Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium sourceToh, E.-H.; Wang, G.H.; Chan, L.; Sylvester, D.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
62008Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applicationsToh, E.-H.; Wang, G.H.; Samudra, G. ; Yeo, Y.-C. 
725-Apr-2008Device physics and performance optimization of impact-ionization metal-oxide-semiconductor transistors formed using a double-spacer fabrication processToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G.S. ; Yeo, Y.-C. 
82008P-channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, in situ doped Si 1-yCy source, and sub-5 mV/decade subthreshold swingToh, E.-H.; Wang, G.H.; Weeks, D.; Zhu, M. ; Bauer, M.; Spear, J.; Chan, L.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
92008Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implantWang, G.H.; Toh, E.-H.; Wang, X.; Seng, D.H.L.; Tripathy, S.; Osipowicz, T. ; Tau, K.C.; Samudra, G. ; Yeo, Y.-C. 
102008Realization of silicon-germanium-tin (SiGeSn) source/ drain stressors by Sn implant and solid phase epitaxy for strain engineering in SiGe channel P-MOSFETsWang, G.H.; Toh, E.-H.; Chan, T.K.; Osipowicz, T.; Foo, Y.-L.; Tung, C.H.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
111-Jan-2008Simulation and design of a germanium L-shaped impact-ionization MOS transistorToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
1225-Apr-2008Strain relaxed high quality silicon-germanium-on-insulator substrates formed by pulsed laser irradiation technologyWang, G.H.; Toh, E.-H.; Wang, X.; Hoe, K.-M.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
13Jan-2008Strained silicon-germanium-on-insulator n-MOSFET with embedded silicon source-and-drain stressorsWang, G.H.; Toh, E.-H.; Du, A.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
142008Uniaxial strained silicon n-FETs on silicon-germanium-on-insulator substrates with an e-Si0.7Ge0.3 stress transfer layer and source/drain stressors for performance enhancementWang, G.H.; Toh, E.-H.; Foo, Y.-L.; Tripathy, S. ; Balakumar, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C.