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|Title:||Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant||Authors:||Wang, G.H.
|Issue Date:||2008||Citation:||Wang, G.H.,Toh, E.-H.,Wang, X.,Seng, D.H.L.,Tripathy, S.,Osipowicz, T.,Tau, K.C.,Samudra, G.,Yeo, Y.-C. (2008). Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant. Digest of Technical Papers - Symposium on VLSI Technology : 207-208. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2008.4588620||Abstract:||We report, for the first time, a simple and cost effective cointegration of strained p and n-FETs using Tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration (the equivalent of adding 35% Ge to SiGe S/D stressors) was achieved in the Si0.7Ge0.3S/D of Si channel p-FET. A significant enhancement of up to 150% in hole mobility and 71% in drive current for a 50nm gate length device was observed. Mono C implanted S/D n-FETs show 19% current drive increase. With the simultaneous integration of Ni based FUSI gate, we provide a highly useful extension to future S/D technology for further ID,sat and mobility improvement. © 2008 IEEE.||Source Title:||Digest of Technical Papers - Symposium on VLSI Technology||URI:||http://scholarbank.nus.edu.sg/handle/10635/84076||ISBN:||9781424418053||ISSN:||07431562||DOI:||10.1109/VLSIT.2008.4588620|
|Appears in Collections:||Staff Publications|
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