Realization of silicon-germanium-tin (SiGeSn) source/ drain stressors by Sn implant and solid phase epitaxy for strain engineering in SiGe channel P-MOSFETs

Abstract

We report the first demonstration of silicon-gerrnanium-tin (SiGeSn) source and drain (S/D) stressors formed by Sn implant and solid-phase epitaxy (SPE). SPE was developed to achieve high levels of Sn substitutionality in SiGe S/D, to induce compressive strain in the channel. No recess etch or epi deposition steps were required, leading to minimal incremental process cost. SiGeSn S/D can be easily integrated in a standard CMOS process. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 6.6% in SiGe S/D, having an equivalent lattice constant to that of Si0.4GC0.6, enhancement of IDsat and bole mobility (μhole) are 48% and 88% respectively, over p-FETs without Sn implant. With the demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement. © 2008 IEEE.