Please use this identifier to cite or link to this item:
https://doi.org/10.1109/LED.2004.826569
| Title: | Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode | Authors: | Zhu, S. Yu, H.Y. Whang, S.J. Chen, J.H. Shen, C. Zhu, C. Lee, S.J. Li, M.F. Chan, D.S.H. Yoo, W.J. Du, A. Tung, C.H. Singh, J. Chin, A. Kwong, D.L. |
Keywords: | High-κ Metal gate MOSFET Schottky |
Issue Date: | May-2004 | Citation: | Zhu, S., Yu, H.Y., Whang, S.J., Chen, J.H., Shen, C., Zhu, C., Lee, S.J., Li, M.F., Chan, D.S.H., Yoo, W.J., Du, A., Tung, C.H., Singh, J., Chin, A., Kwong, D.L. (2004-05). Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode. IEEE Electron Device Letters 25 (5) : 268-270. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2004.826569 | Abstract: | This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff ∼ 107 - 108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, Ion/Ioff can reach ∼ 105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology. | Source Title: | IEEE Electron Device Letters | URI: | http://scholarbank.nus.edu.sg/handle/10635/84422 | ISSN: | 07413106 | DOI: | 10.1109/LED.2004.826569 |
| Appears in Collections: | Staff Publications |
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