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|Title:||Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes||Authors:||Zhu, S.
|Issue Date:||2004||Citation:||Zhu, S.,Chen, J.,Yu, H.Y.,Whang, S.J.,Chen, J.H.,Shen, C.,Li, M.F.,Lee, S.J.,Zhu, C.,Chan, D.S.H.,Du, A.,Tung, C.H.,Singh, J.,Chin, A.,Kwong, D.L. (2004). Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 1 : 53-56. ScholarBank@NUS Repository.||Abstract:||Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO 2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I on ∼10 7-10 8 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi 2-x silicide have also demonstrated a very promising characteristic with a recorded high I on/I off radio of∼ 10 7 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology. © 2004 IEEE.||Source Title:||International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT||URI:||http://scholarbank.nus.edu.sg/handle/10635/84158|
|Appears in Collections:||Staff Publications|
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