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Yee Chia Yeo

rp09882

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Full Name
Yee Chia Yeo
Variants
Yeo, Y.
Yeo Y.-C.
Yeo, Y.C.
Yeo, Y.-C.
Yeo., Y.-C.
 
Main Affiliation
 
Faculty
 
Email
eleyeoyc@nus.edu.sg
 

Publications

Refined By:
Date Issued:  [2000 TO 2023]
Type:  Article
Author:  Samudra, G.

Results 1-20 of 85 (Search time: 0.008 seconds).

Issue DateTitleAuthor(s)
1Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
2Feb-2008A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFETTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
3Mar-2011A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.-T.; Samudra, G. ; Yeo, Y.-C. 
4Jun-2010A simulation study of graphene-nanoribbon tunneling FET with heterojunction channelLam, K.-T.; Seah, D.; Chin, S.-K.; Bala Kumar, S. ; Samudra, G. ; Yeo, Y.-C. ; Liang, G. 
52008A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistorsShen, C.; Ong, S.-L.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
6Apr-2008Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra-narrow fin widthsLee, R.T.-P. ; Liow, T.-Y.; Tan, K.-M.; Lim, A.E.-J.; Koh, A.T.-Y.; Zhu, M. ; Lo, G.-Q.; Samudra, G.S. ; Chi, D.Z.; Yeo, Y.-C. 
72008Band alignment between amorphous Ge2 Sb2 Te5 and prevalent complementary-metal-oxide-semiconductor materialsFang, L.W.-W.; Pan, J.-S.; Zhao, R.; Shi, L.; Chong, T.-C.; Samudra, G. ; Yeo, Y.-C. 
8Nov-2007Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon-carbon source/drain regionsAng, K.-W.; Chin, H.-C.; Chui, K.-J.; Li, M.-F. ; Samudra, G.S. ; Yeo, Y.-C. 
919-Jul-2010Carrier transport in strained N-channel field effect transistors with channel proximate silicon-carbon source/drain stressorsKoh, S.-M.; Samudra, G.S. ; Yeo, Y.-C. 
10Jul-2008Cointegration of in situ doped silicon-carbon source and silicon-carbon I-region in P-channel silicon nanowire impact-ionization transistorToh, E.-H.; Wang, G.H.; Chan, L.; Weeks, D.; Bauer, M.; Spear, J.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
112008Compact HSPICE model for IMOS deviceLin, J. ; Toh, E.H.; Shen, C.; Sylvester, D.; Heng, C.H. ; Samudra, G. ; Yeo, Y.C. 
1225-Apr-2008Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancementWang, G.H.; Toh, E.-H.; Tung, C.-H.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
132009Contact resistance reduction technology using selenium egregation for N-MOSFETs with silicon-carbon source/drainWong, H.-S.; Ang, K.-W.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
14Apr-2012Contact technology for strained nFinFETs with silicon-carbon source/drain stressors featuring sulfur implant and segregationKoh, S.-M.; Samudra, G.S. ; Yeo, Y.-C. 
15Nov-2011Contact-resistance reduction for strained n-FinFETs with silicon-carbon source/drain and platinum-based silicide contacts featuring tellurium implantation and segregationKoh, S.-M.; Kong, E.Y.-J.; Liu, B.; Ng, C.-M.; Samudra, G.S. ; Yeo, Y.-C. 
1625-Apr-2008Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium sourceToh, E.-H.; Wang, G.H.; Chan, L.; Sylvester, D.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
172007Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimizationToh, E.-H.; Wang, G.H.; Samudra, G. ; Yeo, Y.-C. 
182008Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applicationsToh, E.-H.; Wang, G.H.; Samudra, G. ; Yeo, Y.-C. 
192007Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunctionToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
2025-Apr-2008Device physics and performance optimization of impact-ionization metal-oxide-semiconductor transistors formed using a double-spacer fabrication processToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G.S. ; Yeo, Y.-C.