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Samudra,Ganesh S

rp00141

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Full Name
Samudra,Ganesh S
Variants
Samudra, G.G.
SAMUDRA, GANESH SHANKAR
Samudra', G.S.
Samudra, Ganesh S.
Samudra, Ganesh Shankar
Shankar Samudra, Ganesh
Samudra, G.S.
Samudra, Ganesh
Samudra, G.
 
Main Affiliation
 
Faculty
 
Email
eleshanr@nus.edu.sg
 

Publications

Refined By:
Date Issued:  [2000 TO 2009]
Type:  Article

Results 1-20 of 105 (Search time: 0.005 seconds).

Issue DateTitleAuthor(s)
1Oct-2000120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limitXu, S.; Gan, K.P.; Samudra, G.S. ; Liang, Y.C.; Sin, J.K.O.
2Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
3May-2003A dual BARC method for lithography and etch for Dual damascene with low KMukherjee-Roy, M.; Bliznetsov, V.; Samudra, G. 
4Sep-2004A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performanceJagar, S.; Singh, N.; Mehta, S.S.; Agrawal, N.; Samudra, G. ; Balasubramanian, N.
5Feb-2008A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFETTan, K.-M.; Zhu, M. ; Fang, W.-W.; Yang, M.; Liow, T.-Y.; Lee, R.T.P. ; Hoe, K.M.; Tung, C.-H.; Balasubramanian, N.; Samudra, G.S. ; Yeo, Y.-C. 
611-Jun-2008A pseudopotential method for investigating the surface roughness effect in ultrathin body transistorsZhu, Z.-G.; Liang, G. ; Li, M.-F. ; Samudra, G. 
7Oct-2002A simple technology for superjunction device fabrication: Polyflanked VDMOSFETGan, K.P.; Yang, X.; Liang, Y.C. ; Samudra, G.S. ; Yong, L.
82008A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistorsShen, C.; Ong, S.-L.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
9Sep-2003Accurate current sensor for lateral IGBT smart power integrationLiang, Y.C. ; Samudra, G.S. ; Lim, J.D.; Ong, P.H.
10Apr-2008Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra-narrow fin widthsLee, R.T.-P. ; Liow, T.-Y.; Tan, K.-M.; Lim, A.E.-J.; Koh, A.T.-Y.; Zhu, M. ; Lo, G.-Q.; Samudra, G.S. ; Chi, D.Z.; Yeo, Y.-C. 
112008Band alignment between amorphous Ge2 Sb2 Te5 and prevalent complementary-metal-oxide-semiconductor materialsFang, L.W.-W.; Pan, J.-S.; Zhao, R.; Shi, L.; Chong, T.-C.; Samudra, G. ; Yeo, Y.-C. 
12Nov-2007Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon-carbon source/drain regionsAng, K.-W.; Chin, H.-C.; Chui, K.-J.; Li, M.-F. ; Samudra, G.S. ; Yeo, Y.-C. 
132009Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM techniqueZhao, H.; Kim, R.; Paul, A.; Luisier, M.; Klimeck, G.; Ma, F.-J. ; Rustagi, S.C.; Samudra, G.S. ; Singh, N.; Lo, G.-Q.; Kwong, D.-L.
142009Charge-based capacitance measurement technique for nanoscale devices: Accuracy assessment based on TCAD simulationsZhao, H.; Rustagi, S.C.; Ma, F.-J. ; Samudra, G.S. ; Singh, N.; Lo, G.Q.; Kwong, D.-L.
15Jul-2008Cointegration of in situ doped silicon-carbon source and silicon-carbon I-region in P-channel silicon nanowire impact-ionization transistorToh, E.-H.; Wang, G.H.; Chan, L.; Weeks, D.; Bauer, M.; Spear, J.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
162008Compact HSPICE model for IMOS deviceLin, J. ; Toh, E.H.; Shen, C.; Sylvester, D.; Heng, C.H. ; Samudra, G. ; Yeo, Y.C. 
1725-Apr-2008Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancementWang, G.H.; Toh, E.-H.; Tung, C.-H.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
182009Contact resistance reduction technology using selenium egregation for N-MOSFETs with silicon-carbon source/drainWong, H.-S.; Ang, K.-W.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
19Jul-2007Design of gradient oxide-bypassed superjunction power MOSFET devicesChen, Y.; Liang, Y.C. ; Samudra, G.S. 
2025-Apr-2008Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium sourceToh, E.-H.; Wang, G.H.; Chan, L.; Sylvester, D.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C.