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Samudra,Ganesh S

rp00141

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Full Name
Samudra,Ganesh S
Variants
Samudra, G.G.
SAMUDRA, GANESH SHANKAR
Samudra', G.S.
Samudra, Ganesh S.
Samudra, Ganesh Shankar
Shankar Samudra, Ganesh
Samudra, G.S.
Samudra, Ganesh
Samudra, G.
 
Main Affiliation
 
Faculty
 
Email
eleshanr@nus.edu.sg
 

Publications

Refined By:
Date Issued:  [2000 TO 2009]
Author:  Yeo, Y.-C.
Author:  Toh, E.-H.

Results 1-20 of 34 (Search time: 0.006 seconds).

Issue DateTitleAuthor(s)
12008A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performanceToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
2Feb-2008A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performanceToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
32009A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FETShen, C.; Yang, L.T.; Toh, E.-H.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
42005A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistorToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Balasubramanian, N.; Tung, C.-H.; Benistant, F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
52007A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancementToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Choy, S.-F.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
6Jul-2008Cointegration of in situ doped silicon-carbon source and silicon-carbon I-region in P-channel silicon nanowire impact-ionization transistorToh, E.-H.; Wang, G.H.; Chan, L.; Weeks, D.; Bauer, M.; Spear, J.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
725-Apr-2008Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancementWang, G.H.; Toh, E.-H.; Tung, C.-H.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
825-Apr-2008Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium sourceToh, E.-H.; Wang, G.H.; Chan, L.; Sylvester, D.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
92007Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimizationToh, E.-H.; Wang, G.H.; Samudra, G. ; Yeo, Y.-C. 
102008Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applicationsToh, E.-H.; Wang, G.H.; Samudra, G. ; Yeo, Y.-C. 
112007Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunctionToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
1225-Apr-2008Device physics and performance optimization of impact-ionization metal-oxide-semiconductor transistors formed using a double-spacer fabrication processToh, E.-H.; Wang, G.H.; Chan, L.; Samudra, G.S. ; Yeo, Y.-C. 
132007Fabrication of strain relaxed silicon-germanium-on-insulator (Si 0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealingWang, G.H.; Toh, E.-H.; Tung, C.-H.; Foo, Y.-L.; Tripathy, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
142006High quality silicon-germanium-on-insulator wafers fabricated using cyclical thermal oxidation and annealingWang, G.H.; Toh, E.-H.; Foo, Y.-L.; Tung, C.-H.; Choy, S.-F.; Samudra, G. ; Yeo, Y.-C. 
15Dec-2006I-MOS transistor with an elevated silicon-germanium impact-ionization region for bandgap engineeringToh, E.-H.; Wang, G.H.; Chan, L.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
162007Impact ionization nanowire transistor with multiple-gates, silicon-germanium impact ionization region, and sub-5 mV/decade subtheshold swingToh, E.-H.; Wang, G.H.; Zhu, M. ; Shen, C.; Chan, L.; Lo, G.-Q.; Tung, C.-H.; Sylvester, D.; Heng, C.-H. ; Samudra, G. ; Yeo, Y.-C. 
172007On the performance limit of impact-ionization transistorsShen, C.; Lin, J.-Q.; Toh, E.-H.; Chang, K.-F.; Bait, P.; Heng, C.-H. ; Samudra, G.S. ; Yeo, Y.-C. 
182008P-channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, in situ doped Si 1-yCy source, and sub-5 mV/decade subthreshold swingToh, E.-H.; Wang, G.H.; Weeks, D.; Zhu, M. ; Bauer, M.; Spear, J.; Chan, L.; Thomas, S.G.; Samudra, G. ; Yeo, Y.-C. 
192007Performance enhancement of n-channel impact-ionization metal-oxide- semiconductor transistor by strain engineeringToh, E.-H.; Wang, G.H.; Lo, G.-Q.; Chan, L.; Samudra, G. ; Yeo, Y.-C. 
202008Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implantWang, G.H.; Toh, E.-H.; Wang, X.; Seng, D.H.L.; Tripathy, S.; Osipowicz, T. ; Tau, K.C.; Samudra, G. ; Yeo, Y.-C.