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|Title:||A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate||Authors:||Ren, C.
|Issue Date:||Aug-2004||Citation:||Ren, C., Yu, H.Y., Kang, J.F., Wang, X.P., Ma, H.H.H., Yeo, Y.-C., Chan, D.S.H., Li, M.-F., Kwong, D.-L. (2004-08). A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate. IEEE Electron Device Letters 25 (8) : 580-582. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2004.832535||Abstract:||A novel replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO2 gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO2 gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO2, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO2. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of ∼0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO2 gate dielectric. © 2004 IEEE.||Source Title:||IEEE Electron Device Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/81863||ISSN:||07413106||DOI:||10.1109/LED.2004.832535|
|Appears in Collections:||Staff Publications|
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