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|Self-selective multi-terminal memtransistor crossbar array for in-memory computing
Swee Liang Wong
Kah Wee Ang
|American Chemical Society
|Xuewei Feng, Sifan Li, Swee Liang Wong, Shiwun Tong, Li Chen, Zhang Panpan, Lingfei Wang, Xuanyao Fong, Dongzhi Chi, Kah Wee Ang (2021-01-14). Self-selective multi-terminal memtransistor crossbar array for in-memory computing. ACS Nano 15 (1) : 1764-1774. ScholarBank@NUS Repository. https://doi.org/https://doi-org.libproxy1.nus.edu.sg/10.1021/acsnano.0c09441
|Two-terminal resistive switching devices are commonly plagued with longstanding scientific issues including interdevice variability and sneak current that lead to computational errors and high-power consumption. This necessitates the integration of a separate selector in a one-transistor-one-RRAM (1T-1R) configuration to mitigate crosstalk issue, which compromises circuit footprint. Here, we demonstrate a multi-terminal memtransistor crossbar array with increased parallelism in programming via independent gate control, which allows in situ computation at a dense cell size of 3–4.5 F2 and a minimal sneak current of 0.1 nA. Moreover, a low switching energy of 20 fJ/bit is achieved at a voltage of merely 0.42 V. The architecture is capable of performing multiply-and-accumulate operation, a core computing task for pattern classification. A high MNIST recognition accuracy of 96.87% is simulated owing to the linear synaptic plasticity. Such computing paradigm is deemed revolutionary toward enabling data-centric applications in artificial intelligence and Internet-of-things.
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