New insights in hf based high-k gate dielectrics in mosfets

Abstract

I. Two different traps (fast and slow) in HfO 2 gate dielectric are identified. For the slow traps, the negative U (-U) property of trap is proposed and confirmed by the first principle calculation. Each trap can trap two electrons or two holes and lower the trap energy due to a large lattice relaxation. The observed experimental result of reduction in slow component of bias temperature instability (BTI) degradation with an increase in stress frequency can be simulated with excellent agreement, based on the concept of -U. A fast BTI component is also observed. The fast dynamic BTI degradation is increased with an increase in stress frequency. It is due to the existence of fast traps and can be simulated by the conventional trapping/de-trapping equations. The fast trap is a standard conventional trap. II. Mixing Ta and La into HfO 2 to form HfTaO and HfLaO gate dielectric have been studied systematically. Comparing to the HfO 2 gate dielectric, the HfTaO and HfLaO have the advantages of much higher crystallization temperature, much lower charge trapping as well as the BTI degradation, and increased channel mobility. In addition, variation of La concentration in HfLaO/TaN or HfLaO/HfN gate stack can effectively tune the metal work function continuously from mid gap to 4eV. Possible physical explanation for these interesting properties are discussed. copyright The Electrochemical Society.