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https://doi.org/10.1109/ISCAS48785.2022.9937891
Title: | An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning | Authors: | Nguyen, Thao NN Veeravalli, Bharadwaj Fong, Xuanyao |
Keywords: | Science & Technology Technology Engineering, Electrical & Electronic Engineering Spiking Neural Networks Reconfigurable Computing Hardware Accelerator On-Chip Learning MODEL |
Issue Date: | 2022 | Publisher: | IEEE | Citation: | Nguyen, Thao NN, Veeravalli, Bharadwaj, Fong, Xuanyao (2022). An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning. IEEE International Symposium on Circuits and Systems (ISCAS) 2022-May : 2157-2161. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS48785.2022.9937891 | Abstract: | In this paper, we report on the design of a neuromorphic co-processor on a Field Programmable Gate Array (FPGA) platform that is capable of emulating Spiking Neural Networks (SNNs) with support for on-chip unsupervised learning. One defining feature of our design is that the SNN configuration is defined entirely in the software executed by our neuromorphic co-processor. Evaluation on the FPGA platform shows that our design consumes a small amount of hardware resources and on-chip memory storage (438.75 kB). In addition, the inference and the on-chip learning in a deep convolutional SNN emulated on our FPGA implementation are 10.5vf \times and 8.6 \times faster than the implementation on high performance x86 CPU. Moreover, we demonstrate the ability of our neuromorphic co-processor to perform the on-chip learning on an object recognition task (based on the Caltech-101 dataset). | Source Title: | IEEE International Symposium on Circuits and Systems (ISCAS) | URI: | https://scholarbank.nus.edu.sg/handle/10635/245762 | ISBN: | 9781665484855 | ISSN: | 0271-4302 | DOI: | 10.1109/ISCAS48785.2022.9937891 |
Appears in Collections: | Staff Publications Elements |
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