Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS48785.2022.9937891
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dc.titleAn FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
dc.contributor.authorNguyen, Thao NN
dc.contributor.authorVeeravalli, Bharadwaj
dc.contributor.authorFong, Xuanyao
dc.date.accessioned2023-11-06T08:53:19Z
dc.date.available2023-11-06T08:53:19Z
dc.date.issued2022
dc.identifier.citationNguyen, Thao NN, Veeravalli, Bharadwaj, Fong, Xuanyao (2022). An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning. IEEE International Symposium on Circuits and Systems (ISCAS) 2022-May : 2157-2161. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS48785.2022.9937891
dc.identifier.isbn9781665484855
dc.identifier.issn0271-4302
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/245762
dc.description.abstractIn this paper, we report on the design of a neuromorphic co-processor on a Field Programmable Gate Array (FPGA) platform that is capable of emulating Spiking Neural Networks (SNNs) with support for on-chip unsupervised learning. One defining feature of our design is that the SNN configuration is defined entirely in the software executed by our neuromorphic co-processor. Evaluation on the FPGA platform shows that our design consumes a small amount of hardware resources and on-chip memory storage (438.75 kB). In addition, the inference and the on-chip learning in a deep convolutional SNN emulated on our FPGA implementation are 10.5vf \times and 8.6 \times faster than the implementation on high performance x86 CPU. Moreover, we demonstrate the ability of our neuromorphic co-processor to perform the on-chip learning on an object recognition task (based on the Caltech-101 dataset).
dc.publisherIEEE
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectEngineering, Electrical & Electronic
dc.subjectEngineering
dc.subjectSpiking Neural Networks
dc.subjectReconfigurable Computing
dc.subjectHardware Accelerator
dc.subjectOn-Chip Learning
dc.subjectMODEL
dc.typeConference Paper
dc.date.updated2023-11-05T09:03:52Z
dc.contributor.departmentELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi10.1109/ISCAS48785.2022.9937891
dc.description.sourcetitleIEEE International Symposium on Circuits and Systems (ISCAS)
dc.description.volume2022-May
dc.description.page2157-2161
dc.published.statePublished
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