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Samudra,Ganesh S

rp00141

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Full Name
Samudra,Ganesh S
Variants
Samudra, G.G.
SAMUDRA, GANESH SHANKAR
Samudra', G.S.
Samudra, Ganesh S.
Samudra, Ganesh Shankar
Shankar Samudra, Ganesh
Samudra, G.S.
Samudra, Ganesh
Samudra, G.
 
Main Affiliation
 
Faculty
 
Email
eleshanr@nus.edu.sg
 

Publications

Refined By:
Author:  Samudra, G.
Department:  ELECTRICAL AND COMPUTER ENGINEERING
Author:  Toh, E.-H.
Author:  Tripathy, S.

Results 1-9 of 9 (Search time: 0.003 seconds).

Issue DateTitleAuthor(s)
125-Apr-2008Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancementWang, G.H.; Toh, E.-H.; Tung, C.-H.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
22007Fabrication of strain relaxed silicon-germanium-on-insulator (Si 0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealingWang, G.H.; Toh, E.-H.; Tung, C.-H.; Foo, Y.-L.; Tripathy, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
32008Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implantWang, G.H.; Toh, E.-H.; Wang, X.; Seng, D.H.L.; Tripathy, S.; Osipowicz, T. ; Tau, K.C.; Samudra, G. ; Yeo, Y.-C. 
42007Silicon-germanium-tin (SiGeSn) source and drain stressors formed by Sn implant and laser annealing for strained silicon-germanium channel P-MOSFETsWang, G.H.; Toh, E.-H.; Wang, X.; Seng, D.H.L.; Tripathy, S.; Osipowicz, T.; Chan, T.K.; Hoe, K.M.; Balakumar, S.; Tung, C.H.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
525-Apr-2008Strain relaxed high quality silicon-germanium-on-insulator substrates formed by pulsed laser irradiation technologyWang, G.H.; Toh, E.-H.; Wang, X.; Hoe, K.-M.; Tripathy, S.; Samudra, G.S. ; Yeo, Y.-C. 
62007Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealingWang, G.H.; Toh, E.-H.; Wang, X.; Tripathy, S.; Osipowicz, T. ; Chan, T.K. ; Hoe, K.-M.; Balakumar, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
72006Strained silicon-germanium-on-insulator N-MOSFETs featuring lattice mismatched source/drain stressor and high-stress silicon nitride linerWang, G.H.; Toh, E.-H.; Toh; Hoe, K.M.; Tripathy, S.; Balakurnar, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
82007Sub 50nm strained n-FETs formed on silicon-germanium-on-insulator substrates and the integration of silicon source/drain stressorsWang, G.H.; Toh, E.-H.; Hoe, K.-M.; Tripathy, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C. 
92008Uniaxial strained silicon n-FETs on silicon-germanium-on-insulator substrates with an e-Si0.7Ge0.3 stress transfer layer and source/drain stressors for performance enhancementWang, G.H.; Toh, E.-H.; Foo, Y.-L.; Tripathy, S. ; Balakumar, S.; Lo, G.-Q.; Samudra, G. ; Yeo, Y.-C.