Please use this identifier to cite or link to this item:
|Title:||Fast optical proximity correction with timing optimization ready standard cells||Authors:||Qu, Y.
design for manufacturability (DFM)
Optical proximity correction (OPC)
|Issue Date:||2012||Citation:||Qu, Y., Heng, C.H., Tay, A., Lee, T.H. (2012). Fast optical proximity correction with timing optimization ready standard cells. Proceedings of SPIE - The International Society for Optical Engineering 8327 : -. ScholarBank@NUS Repository. https://doi.org/10.1117/12.916124||Abstract:||Resolution enhancement techniques (RET) such as optical proximity correction (OPC) has become an integral part of the fabrication of integrated circuits to maintain the edge placement integrity of the original circuit design. Conventional OPC schemes are usually shape driven and full chip based, resulting in unpredictability in electrical behavior and huge computational effort. To overcome these drawbacks, a new OPC methodology which is electrically driven and based on cell-wise optimization is proposed. Simulation results when compared to conventional OPC approaches in the literature demonstrate better timing accuracy with reduced mask cost. Depending of the circuit test-set, an average run-time improvement between 3 to 8 times is achieved for circuit size with 100 - 400 cells. Further improvements can be obtained by adopting a hybrid approach by only optimizing the timing performance of critical paths. For the hybrid approach, better timing accuracy can be achieved while incurring little penalty on mask cost. © 2012 Copyright SPIE.||Source Title:||Proceedings of SPIE - The International Society for Optical Engineering||URI:||http://scholarbank.nus.edu.sg/handle/10635/83733||ISBN:||9780819489838||ISSN:||1996756X||DOI:||10.1117/12.916124|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.