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|Title:||A novel floating gate engineering technique for improved data retention of flash memory devices||Authors:||Pu, J.
|Issue Date:||2008||Citation:||Pu, J., Chan, D.S.H., Cho, B.J. (2008). A novel floating gate engineering technique for improved data retention of flash memory devices. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT : 839-842. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2008.4734673||Abstract:||We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells. © 2008 IEEE.||Source Title:||International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT||URI:||http://scholarbank.nus.edu.sg/handle/10635/83398||ISBN:||9781424421855||DOI:||10.1109/ICSICT.2008.4734673|
|Appears in Collections:||Staff Publications|
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