Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICSICT.2008.4734673
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dc.titleA novel floating gate engineering technique for improved data retention of flash memory devices
dc.contributor.authorPu, J.
dc.contributor.authorChan, D.S.H.
dc.contributor.authorCho, B.J.
dc.date.accessioned2014-10-07T04:40:46Z
dc.date.available2014-10-07T04:40:46Z
dc.date.issued2008
dc.identifier.citationPu, J., Chan, D.S.H., Cho, B.J. (2008). A novel floating gate engineering technique for improved data retention of flash memory devices. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT : 839-842. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2008.4734673
dc.identifier.isbn9781424421855
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83398
dc.description.abstractWe propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ICSICT.2008.4734673
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ICSICT.2008.4734673
dc.description.sourcetitleInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
dc.description.page839-842
dc.identifier.isiut000265971001055
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