Please use this identifier to cite or link to this item:
|Title:||A novel floating gate engineering technique for improved data retention of flash memory devices|
|Authors:||Pu, J. |
|Citation:||Pu, J., Chan, D.S.H., Cho, B.J. (2008). A novel floating gate engineering technique for improved data retention of flash memory devices. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT : 839-842. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2008.4734673|
|Abstract:||We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells. © 2008 IEEE.|
|Source Title:||International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jun 22, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.