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|Title:||In situ surface passivation and CMOS-compatible palladium-germanium contacts for surface-channel gallium arsenide MOSFETs||Authors:||Chin, H.-C.
III-V compound semiconductors
Semiconductor device fabrication
|Issue Date:||Jun-2008||Citation:||Chin, H.-C., Zhu, M., Tung, C.-H., Samudra, G.S., Yeo, Y.-C. (2008-06). In situ surface passivation and CMOS-compatible palladium-germanium contacts for surface-channel gallium arsenide MOSFETs. IEEE Electron Device Letters 29 (6) : 553-556. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2008.921393||Abstract:||In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/ HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane treatment), alternative gold-free palladium-germanium (PdGe) source and drain (S/D) ohmic contacts, and silicon plus phosphorus coimplanted S/D regions. With the novel in situ surface passivation, excellent capacitance-voltage characteristics with low-frequency dispersion and small stretch-out can be achieved, indicating low interface state density. This surface-channel GaAs device exhibits excellent transistor output characteristics with a high drain current on/ off ratio of 105 and a high peak electron mobility of 1230 cm2/V · s. In addition, gold contamination concerning CMOS technology can be alleviated with the successful integration of low-resistance PdGe ohmic contacts. © 2008 IEEE.||Source Title:||IEEE Electron Device Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/82520||ISSN:||07413106||DOI:||10.1109/LED.2008.921393|
|Appears in Collections:||Staff Publications|
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