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|Title:||Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-κ gate dielectric and metal gate||Authors:||Zhu, S.
|Keywords:||Low temperature process
Schottky barrier source/drain
|Issue Date:||Feb-2006||Citation:||Zhu, S., Singh, J., Zhu, C., Du, A., Li, M.F. (2006-02). Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-κ gate dielectric and metal gate. Solid-State Electronics 50 (2) : 232-236. ScholarBank@NUS Repository. https://doi.org/10.1016/j.sse.2005.11.001||Abstract:||In this paper, a polycrystalline Si thin film transistor (TFT) with self-aligned silicide Schottky barrier source/drain (SSD), high-κ gate dielectric and metal gate electrode is demonstrated using a simplified low temperature process. After crystallization of α-Si, the thermal budget for device fabrication is reduced to ∼420 °C due to elimination of the implant doping and subsequent activation annealing procedures. P-channel SSD-TFT with PtSi S/D shows an acceptable electrical performance with I on of 1.5 μA/μm for the Lg = 2.5 μm device at Vgs = Vds = -5 V and Ion/Ioff ratio of ∼104. However, Ion of the n-channel SSD-TFT with DySi2-x S/D is about two orders of magnitude smaller due to the relatively high Schottky barrier height and poor silicide quality of the DySi2-x/poly-Si contact. © 2005 Elsevier Ltd. All rights reserved.||Source Title:||Solid-State Electronics||URI:||http://scholarbank.nus.edu.sg/handle/10635/82338||ISSN:||00381101||DOI:||10.1016/j.sse.2005.11.001|
|Appears in Collections:||Staff Publications|
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