Modeling of tunneling currents through HfO2 and (HfO2)x(Al2O3)1-x gate stacks

Abstract

We present a physical modeling of tunneling currents through ultrathin high-k gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-k dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO2 with and without NH3-based Interface layers, and ALD Al2O3 gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO2)x(Al2O3)1-x gate stacks in order to project their scalability for future CMOS applications.