IPC-driven energy reduction for low-power design

Abstract

Energy consumption is one of the most important design constraints for modern microprocessors, and designers have proposed many energy-saving techniques. This paper describes an interval-based identification and prediction mechanism for microprocessors energy reduction. Our mechanism employs a statistical sampling method during current interval run to identify its performance activity level in term of IPC (Instruction per Cycle) values and predict the future interval that could make contributions to processor runtime energy reduction by dynamically scaling the microprocessor voltage and frequency accordingly. In simulation, our approach achieves energy savings by an average of 29% with minor performance degradation, compared to a processor running at a fixed voltage and speed. © 2006 IEEE.