Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/70696
Title: IPC-driven energy reduction for low-power design
Authors: Xia, X.X.
Tay, T.T. 
Issue Date: 2006
Source: Xia, X.X.,Tay, T.T. (2006). IPC-driven energy reduction for low-power design. Proceedings - IEEE International Symposium on Circuits and Systems : 3646-3649. ScholarBank@NUS Repository.
Abstract: Energy consumption is one of the most important design constraints for modern microprocessors, and designers have proposed many energy-saving techniques. This paper describes an interval-based identification and prediction mechanism for microprocessors energy reduction. Our mechanism employs a statistical sampling method during current interval run to identify its performance activity level in term of IPC (Instruction per Cycle) values and predict the future interval that could make contributions to processor runtime energy reduction by dynamically scaling the microprocessor voltage and frequency accordingly. In simulation, our approach achieves energy savings by an average of 29% with minor performance degradation, compared to a processor running at a fixed voltage and speed. © 2006 IEEE.
Source Title: Proceedings - IEEE International Symposium on Circuits and Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/70696
ISBN: 0780393902
ISSN: 02714310
Appears in Collections:Staff Publications

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