Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/70696
DC FieldValue
dc.titleIPC-driven energy reduction for low-power design
dc.contributor.authorXia, X.X.
dc.contributor.authorTay, T.T.
dc.date.accessioned2014-06-19T03:15:09Z
dc.date.available2014-06-19T03:15:09Z
dc.date.issued2006
dc.identifier.citationXia, X.X.,Tay, T.T. (2006). IPC-driven energy reduction for low-power design. Proceedings - IEEE International Symposium on Circuits and Systems : 3646-3649. ScholarBank@NUS Repository.
dc.identifier.isbn0780393902
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70696
dc.description.abstractEnergy consumption is one of the most important design constraints for modern microprocessors, and designers have proposed many energy-saving techniques. This paper describes an interval-based identification and prediction mechanism for microprocessors energy reduction. Our mechanism employs a statistical sampling method during current interval run to identify its performance activity level in term of IPC (Instruction per Cycle) values and predict the future interval that could make contributions to processor runtime energy reduction by dynamically scaling the microprocessor voltage and frequency accordingly. In simulation, our approach achieves energy savings by an average of 29% with minor performance degradation, compared to a processor running at a fixed voltage and speed. © 2006 IEEE.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.page3646-3649
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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