Please use this identifier to cite or link to this item:
|Title:||Impact of metal gate work function on nano CMOS device performance||Authors:||Hou, Y.T.
|Issue Date:||2004||Citation:||Hou, Y.T.,Low, T.,Xu, B.,Li, M.-F.,Samudra, G.,Kwong, D.L. (2004). Impact of metal gate work function on nano CMOS device performance. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 1 : 57-60. ScholarBank@NUS Repository.||Abstract:||We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) We presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed. © 2004 IEEE.||Source Title:||International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT||URI:||http://scholarbank.nus.edu.sg/handle/10635/70537|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Sep 8, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.