Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/70537
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dc.titleImpact of metal gate work function on nano CMOS device performance
dc.contributor.authorHou, Y.T.
dc.contributor.authorLow, T.
dc.contributor.authorXu, B.
dc.contributor.authorLi, M.-F.
dc.contributor.authorSamudra, G.
dc.contributor.authorKwong, D.L.
dc.date.accessioned2014-06-19T03:13:17Z
dc.date.available2014-06-19T03:13:17Z
dc.date.issued2004
dc.identifier.citationHou, Y.T.,Low, T.,Xu, B.,Li, M.-F.,Samudra, G.,Kwong, D.L. (2004). Impact of metal gate work function on nano CMOS device performance. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 1 : 57-60. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70537
dc.description.abstractWe studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) We presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed. © 2004 IEEE.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
dc.description.volume1
dc.description.page57-60
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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