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https://scholarbank.nus.edu.sg/handle/10635/70537
DC Field | Value | |
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dc.title | Impact of metal gate work function on nano CMOS device performance | |
dc.contributor.author | Hou, Y.T. | |
dc.contributor.author | Low, T. | |
dc.contributor.author | Xu, B. | |
dc.contributor.author | Li, M.-F. | |
dc.contributor.author | Samudra, G. | |
dc.contributor.author | Kwong, D.L. | |
dc.date.accessioned | 2014-06-19T03:13:17Z | |
dc.date.available | 2014-06-19T03:13:17Z | |
dc.date.issued | 2004 | |
dc.identifier.citation | Hou, Y.T.,Low, T.,Xu, B.,Li, M.-F.,Samudra, G.,Kwong, D.L. (2004). Impact of metal gate work function on nano CMOS device performance. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 1 : 57-60. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/70537 | |
dc.description.abstract | We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) We presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed. © 2004 IEEE. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.sourcetitle | International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT | |
dc.description.volume | 1 | |
dc.description.page | 57-60 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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