An Energy-Efficient Processing Element Design for Coarse-Grained Reconfigurable Architecture on FPGA

Abstract

Nowadays, energy-efficient devices with high performance and flexibility are desired in different applications. Therefore, the novel coarse-grained reconfigurable architectures (CGRAs) are introduced to reach a balance between performance, power, and programmability. As the key components of CGRAs, processing elements (PEs) with low power consumption are significant to implement energy-efficient CGRAs. In this paper, we present an energy-efficient PE design for CGRAs targeting wearable and Internet-of-Things (IoT) applications. By applying multiplexer gated inputs to the arithmetic logic unit (ALU) and integrating the controller circuit, the power consumption of the proposed PE design in active modes is reduced by 19.06%. With the clock generator being mapped to Mixed Mode Clock Manager (MMCM) module and SRAM being mapped to the block ram module, the FPGA emulation of the PE block is success on the evaluation board.