Exploring variability and reliability of multi-level STT-MRAM cells

Abstract

Multi-level spin-transfer torque magnetoresistive random access memory (STT-MRAM) has been proposed to improve bit-density, power consumption and speed of standard STT-MRAM. The traditional STT-MRAM bit-cell consists of one access transistor and one magnetic tunnel junction (MTJ) (1T-1R) [1] whereas multi-level STT-MRAM has two stacked MTJs with one access transistor (1T-2R, see Fig. 1) as proposed in [2]. However, variability and reliability issues can degrade the benefits associated with multi-level STT-MRAM. The variability issues in 1T-2R are attributed to the process variations in both the access transistor and the MTJs [3]. The primary reliability concern in 1T-2R is the time-dependent dielectric breakdown (TDDB) of the tunnel junction (MgO) in the MTJ [4]. TDDB lowers lifetime and can further degrade the performance of the MTJ cell with MgO thickness scaling [4]. Hence, in this paper we present in-depth study of variability and reliability of multi-level STT-MRAM cells. We also propose device/circuit optimization techniques for design space analysis of 1T-2R cell. © 2012 IEEE.