Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2016.7527390
Title: A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks
Authors: Narasimman, Govind
Roy, Subhrajit
Fong, Xuanyao 
Roy, Kaushik
Chang, Chip-Hong
Basu, Arindam
Keywords: Science & Technology
Technology
Engineering, Electrical & Electronic
Engineering
PLASTICITY
Issue Date: 1-Jan-2016
Publisher: IEEE
Citation: Narasimman, Govind, Roy, Subhrajit, Fong, Xuanyao, Roy, Kaushik, Chang, Chip-Hong, Basu, Arindam (2016-01-01). A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks. IEEE International Symposium on Circuits and Systems (ISCAS) 2016-July : 914-917. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2016.7527390
Abstract: © 2016 IEEE. Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However, these approaches require high voltages (≈ 3-12V) for weight update and entail high energy for learning (≈ 4-30pJ/write). We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈ 40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.
Source Title: IEEE International Symposium on Circuits and Systems (ISCAS)
URI: https://scholarbank.nus.edu.sg/handle/10635/156200
ISBN: 9781479953400
ISSN: 0271-4302
DOI: 10.1109/ISCAS.2016.7527390
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