Please use this identifier to cite or link to this item: https://doi.org/10.1109/TMAG.2014.2326858
Title: Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective
Authors: Fong, Xuanyao 
Venkatesan, Rangharajan
Raghunathan, Anand
Roy, Kaushik
Keywords: Science & Technology
Technology
Physical Sciences
Engineering, Electrical & Electronic
Physics, Applied
Engineering
Physics
Complementary polarizer spin-transfer torque magnetic random access memory (CPSTT-MRAM)
spin-transfer torque magnetic random access memory (STT-MRAM)
symmetric STT-MRAM write current
true self-reference differential STT-MRAM
MAGNETIC TUNNEL-JUNCTIONS
STT-MRAMS
MAGNETORESISTANCE
SCHEME
RAM
Issue Date: 1-Oct-2014
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: Fong, Xuanyao, Venkatesan, Rangharajan, Raghunathan, Anand, Roy, Kaushik (2014-10-01). Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective. IEEE TRANSACTIONS ON MAGNETICS 50 (10). ScholarBank@NUS Repository. https://doi.org/10.1109/TMAG.2014.2326858
Abstract: © 1965-2012 IEEE. In this paper, we propose a new spin-transfer torque magnetic random access memory (STT-MRAM) bit-cell structure (with complementary polarizers) that is suitable for on-chip caches. Our proposed structure requires a lower average critical write current than standard STT-MRAM, with improved write-ability, readability, and reliability. A cache array based on our proposed structure is studied using a device/circuit simulation framework, which we developed for this paper. Simulation results show that at the bit-cell level, our proposed structure can achieve subnanosecond sensing delay and lower read disturb torque using a self-referenced differential READ operation. Sensing and disturb margins of our proposed cell are \(1.8× \) and \(2.4× ) better than standard STT-MRAM, respectively. Furthermore, near disturb-free READ operation at ≥1.5 GHz is achieved using a latch-based sense amplifier and verified in circuit simulations. In addition, content addressable memory may also be efficiently implemented using complementary polarizer spin-transfer torque (CPSTT). Transient SPICE simulations show that CPSTT may be suitable for L1 cache, with a read energy of 14 fJ/bit. System level simulation shows that a CPSTT-based L2 cache can achieve (∼ 9) % lower energy consumption and >9% improvement in instructions per cycle over a standard STT-MRAM-based cache.
Source Title: IEEE TRANSACTIONS ON MAGNETICS
URI: https://scholarbank.nus.edu.sg/handle/10635/156183
ISSN: 0018-9464
1941-0069
DOI: 10.1109/TMAG.2014.2326858
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