Please use this identifier to cite or link to this item:
https://doi.org/10.1109/TMAG.2014.2326858
DC Field | Value | |
---|---|---|
dc.title | Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective | |
dc.contributor.author | Fong, Xuanyao | |
dc.contributor.author | Venkatesan, Rangharajan | |
dc.contributor.author | Raghunathan, Anand | |
dc.contributor.author | Roy, Kaushik | |
dc.date.accessioned | 2019-07-03T03:31:18Z | |
dc.date.available | 2019-07-03T03:31:18Z | |
dc.date.issued | 2014-10-01 | |
dc.identifier.citation | Fong, Xuanyao, Venkatesan, Rangharajan, Raghunathan, Anand, Roy, Kaushik (2014-10-01). Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective. IEEE TRANSACTIONS ON MAGNETICS 50 (10). ScholarBank@NUS Repository. https://doi.org/10.1109/TMAG.2014.2326858 | |
dc.identifier.issn | 0018-9464 | |
dc.identifier.issn | 1941-0069 | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/156183 | |
dc.description.abstract | © 1965-2012 IEEE. In this paper, we propose a new spin-transfer torque magnetic random access memory (STT-MRAM) bit-cell structure (with complementary polarizers) that is suitable for on-chip caches. Our proposed structure requires a lower average critical write current than standard STT-MRAM, with improved write-ability, readability, and reliability. A cache array based on our proposed structure is studied using a device/circuit simulation framework, which we developed for this paper. Simulation results show that at the bit-cell level, our proposed structure can achieve subnanosecond sensing delay and lower read disturb torque using a self-referenced differential READ operation. Sensing and disturb margins of our proposed cell are \(1.8× \) and \(2.4× ) better than standard STT-MRAM, respectively. Furthermore, near disturb-free READ operation at ≥1.5 GHz is achieved using a latch-based sense amplifier and verified in circuit simulations. In addition, content addressable memory may also be efficiently implemented using complementary polarizer spin-transfer torque (CPSTT). Transient SPICE simulations show that CPSTT may be suitable for L1 cache, with a read energy of 14 fJ/bit. System level simulation shows that a CPSTT-based L2 cache can achieve (∼ 9) % lower energy consumption and >9% improvement in instructions per cycle over a standard STT-MRAM-based cache. | |
dc.language.iso | en | |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |
dc.source | Elements | |
dc.subject | Science & Technology | |
dc.subject | Technology | |
dc.subject | Physical Sciences | |
dc.subject | Engineering, Electrical & Electronic | |
dc.subject | Physics, Applied | |
dc.subject | Engineering | |
dc.subject | Physics | |
dc.subject | Complementary polarizer spin-transfer torque magnetic random access memory (CPSTT-MRAM) | |
dc.subject | spin-transfer torque magnetic random access memory (STT-MRAM) | |
dc.subject | symmetric STT-MRAM write current | |
dc.subject | true self-reference differential STT-MRAM | |
dc.subject | MAGNETIC TUNNEL-JUNCTIONS | |
dc.subject | STT-MRAMS | |
dc.subject | MAGNETORESISTANCE | |
dc.subject | SCHEME | |
dc.subject | RAM | |
dc.type | Article | |
dc.date.updated | 2019-07-03T03:09:49Z | |
dc.contributor.department | ELECTRICAL AND COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/TMAG.2014.2326858 | |
dc.description.sourcetitle | IEEE TRANSACTIONS ON MAGNETICS | |
dc.description.volume | 50 | |
dc.description.issue | 10 | |
dc.published.state | Published | |
Appears in Collections: | Staff Publications Elements |
Show simple item record
Files in This Item:
File | Description | Size | Format | Access Settings | Version | |
---|---|---|---|---|---|---|
Fong et al. - 2014 - Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches A DeviceCircuitSystems Perspective.pdf | Published version | 3.8 MB | Adobe PDF | CLOSED | Published |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.