Please use this identifier to cite or link to this item:
https://doi.org/10.1109/LED.2012.2234079
| Title: | Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches | Authors: | Fong, Xuanyao Roy, Kaushik |
Keywords: | Science & Technology Technology Engineering, Electrical & Electronic Engineering Improved dual pillar STT-MRAM spin-transfer torque MRAM (STT-MRAM) symmetric STT-MRAM write current true self-reference differential STT-MRAM |
Issue Date: | 1-Feb-2013 | Publisher: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | Citation: | Fong, Xuanyao, Roy, Kaushik (2013-02-01). Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches. IEEE ELECTRON DEVICE LETTERS 34 (2) : 232-234. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2012.2234079 | Abstract: | Spin-transfer torque magnetic random access memory devices (STT-MRAMs) show great promise as a candidate technology for on-chip caches. In this letter, we propose a new STT-MRAM bit-cell structure that is suitable for on-chip caches compared with the standard STT-MRAM bit-cell (SSC). Scalability of our proposed structure is studied with the aid of micromagnetic and circuit simulators. Results show that our proposed bit-cell is more scalable than the SSC, achieving >4× better write margin, > 65% better sensing margin, lower read disturb failures, and subnanosecond sensing delays. © 1980-2012 IEEE. | Source Title: | IEEE ELECTRON DEVICE LETTERS | URI: | https://scholarbank.nus.edu.sg/handle/10635/156165 | ISSN: | 07413106 15580563 |
DOI: | 10.1109/LED.2012.2234079 |
| Appears in Collections: | Staff Publications Elements |
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| File | Description | Size | Format | Access Settings | Version | |
|---|---|---|---|---|---|---|
| Fong, Roy - 2013 - Complementary Polarizers STT-MRAM (CPSTT) for On-Chip Caches.pdf | Published version | 1.01 MB | Adobe PDF | CLOSED | None |
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