Please use this identifier to cite or link to this item: https://doi.org/10.1109/TNANO.2011.2169456
Title: Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
Authors: Fong, Xuanyao 
Choday, Sri Harsha
Roy, Kaushik 
Keywords: Science & Technology
Technology
Physical Sciences
Engineering, Electrical & Electronic
Nanoscience & Nanotechnology
Materials Science, Multidisciplinary
Physics, Applied
Engineering
Science & Technology - Other Topics
Materials Science
Physics
Circuit optimization
magnetic memories
magnetic tunnel junctions (MTJ)
memory architectures
spin-transfer torque MRAM (STT-MRAM) bit-cells
Issue Date: 1-Jan-2012
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: Fong, Xuanyao, Choday, Sri Harsha, Roy, Kaushik (2012-01-01). Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching. IEEE TRANSACTIONS ON NANOTECHNOLOGY 11 (1) : 172-181. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2011.2169456
Abstract: Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Greens Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45nm bulk and 45nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16nm predictive technology. © 2011 IEEE.
Source Title: IEEE TRANSACTIONS ON NANOTECHNOLOGY
URI: https://scholarbank.nus.edu.sg/handle/10635/156164
ISSN: 1536125X
19410085
DOI: 10.1109/TNANO.2011.2169456
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