Please use this identifier to cite or link to this item:
https://doi.org/10.1109/IEDM.2006.346840
| Title: | Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance | Authors: | Singh, N. Lim, F.Y. Fang, W.W. Rustagi, S.C. Bera, L.K. Agarwal, A. Tung, C.H. Hoe, K.M. Omampuliyur, S.R. Tripathi, D. Adeyeye, A.O. Lo, G.Q. Balasubramanian, N. Kwong, D.L. |
Issue Date: | 2006 | Citation: | Singh, N.,Lim, F.Y.,Fang, W.W.,Rustagi, S.C.,Bera, L.K.,Agarwal, A.,Tung, C.H.,Hoe, K.M.,Omampuliyur, S.R.,Tripathi, D.,Adeyeye, A.O.,Lo, G.Q.,Balasubramanian, N.,Kwong, D.L. (2006). Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. Technical Digest - International Electron Devices Meeting, IEDM : -. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2006.346840 | Abstract: | Fully CMOS compatible Silicon-nanowire (SiNW) Gate-All-Around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/μm for n-FET, 1.3 mA/μm for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-V8 oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well. | Source Title: | Technical Digest - International Electron Devices Meeting, IEDM | URI: | http://scholarbank.nus.edu.sg/handle/10635/84334 | ISBN: | 1424404398 | ISSN: | 01631918 | DOI: | 10.1109/IEDM.2006.346840 |
| Appears in Collections: | Staff Publications |
Show full item record
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.