Strained channel transistor using strain field induced by source and drain stressors

Abstract

We perform a theoretical evaluation of the strain field in a p-channel transistor with silicon-germanium (Si 1-yGe y) stressors in the source and drain regions. The strain field comprises a lateral compressive strain component and a vertical tensile strain component. The lateral strain component is larger in magnitude and more uniformly distributed as compared to the vertical strain component. The impact of transistor design parameters, such as the Ge mole fraction y in the stressors, the spacing L between stressors, the stressor depth, and the raised stressor height, on the strain field are investigated. Hole mobility enhancement larger than 30% is achievable wth L = 50 nm and y = 0.15. More aggressive mobility enhancement targets may be achievable by reducing the stressor spacing and employing a stressor with a larger lattice mismatch with the Si channel.