A 1.2 V rail-to-rail differential mode input linear CMOS transconductor

Abstract

Rail-to-rail differential mode input capability in low voltage CMOS transconductor design is implemented by a pull-down and a pull-up follower in an input buffer. By generating three intermediate voltages in the buffer stage, three voltages are converted to three currents and subsequently summed using MOSFETSs operating in the triode region. The nonlinear current components can be cancelled completely. The lowest supply voltage Vdd is constrained by 2Vth of the MOS transistors. A single 1.2V operational transconductor amplifier (OTA) was designed using 0.35μm CMOS technology and the simulated I-V linearity error is less than 1% within the rail-to-rail differential input range. The achieved THD is less than 0.6% for a 1 KHz, 1.2 Vpp input signal.